New-Tech Europe Magazine | Aug 2018

As with many design challenges, there are several ways to address the problem: PCB Layout Designers can alleviate some of these conditions by being strategic about their board layout. Well- planned trace design and routings, location of grounds, vias, etc., improve PCB data rates. PCB design strategies are beyond the scope of this article, but numerous tools, resources, and personnel exist to assist in this endeavor. Samtec, for example, has the Signal Integrity Group and Teraspeed Consulting to assist in these matters. Interconnect Design Although the goals of miniaturization and higher data rates conflict, connector manufacturers can strike a balance in performance and footprint size. One example of these connector design strategies is a contact called Edge Rate®. This contact is designed for higher cycle applications while accommodating higher bandwidths. For example, the .8mm pitch Edge Rate interconnect is rated at 56 Gbps PAM4. One of the ways it achieves this balance between bandwidth and pitch is the design and placement of the pins in the plastic body. Specifically, the thin, narrow, cut edges of the Edge Rage contact are positioned side-by-side. This minimizes the parallel surface areas, which reduces broadside coupling and crosstalk. Improving Connector Performance Other connector design strategies to achieve high-bandwidth, micro pitch High-Speed, Micro Pitch

Figure 1: High-speed, micro pitch Edge Rate ® socket. Improving Connector Performance

connector as a critical node in the link; focus not just on the node, but the link Incorporate common ground planes into the connector, space permitting The choice of plastic molding obviously affects connector performance. Among other concerns, we carefully consider the following attributes - High temperature plastic for RoHS -Matching Dk for the desired impedance control - Dimensional stability over temperature and time The bottom line is, the shorter and straighter the signal path (and connector contact), the better the signal integrity performance. But the balancing act is the connector must have adequate normal force and withdrawal force, as well as have a certain degree of ruggedness. The latter considerations usually detract for the signal integrity performance.

interconnects include, but are not limited to: Perform multiple simulation cycles in the early stages of the design, in order to accurately quantify product performance before you begin the expensive tooling process Minimize the stub in the contact area when the connector is mated. Mechanically, the longer the stub the better for reliability, but the longer stub is an electrical liability acting like an antenna. Simplify contact geometry for improved signal path performance Shorten the pin length to minimize the distance the signal must travel Incorporate, where possible, asymmetrical footprints and contacts; alternating designs decrease crosstalk from pair-to-pair within the row of pins and between rows. Said another way, the footprint should drive the connector performance Optimize the connector Break Out Region (BOR). Think of the

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