New-Tech Europe Magazine | October 2018

Figure 1. FLX-1200 platform dedicated for pilot R&D picture and basic operation schemes

The technology’s suitability for insertion in existing silicon-chip manufacturing has been demonstrated directly on product wafers manufactured in a conventional IC fab [1]. This first customer demo involved wafers from a mature industrial CMOS N40 flow at via-3 level with copper- based interconnects (BEOL). The product wafers were exposed on the FLX-1200 multi beam tool at 5kV by printing the metrology blocks located in the corner of the frame multibeam

versus several-days equivalent for conventional single e-beam tools). So by taking advantage of direct write’s flexibility and the associated cost benefits of maskless lithography, this technology can address a wide range of end markets. These include: R&D, prototyping and small series CMOS runs Fab capability expansion (e.g. use of maskless litho to push existing fab capability to more advanced technology nodes)

Integrated CMOS sensor optics Patterning of large surface areas. This technology becomes even more attractive when flexibility can be pushed to its maximum by exposing a design layout modified for each individual chip. Designers can modify a functionality and/ or insert a unique code into each product (Figure 2). Maskless litho can efficiently address the greater demand for diverse and hardware- secure solutions to prevent chip cloning and reverse engineering.

Figure 2. Wafer exposure strategy • With repeated identical chips on optical scanner • With diversified unique chips with Mapper FLX-1200 tool

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