New-Tech Europe Magazine | October 2018

Realizing 5G New Radio Massive MIMO Systems

Paul Newson, Hemang Parekh, Harpinder Matharu, Xilinx

The promise of Massive MIMO is so appealing that many operators do not want to wait for the 5G NR ecosystem to be ready and are considering deploying it on 4G equipment. However, its many benefits come with a set of challenges. The larger footprint, higher power and greater cost due to the multifold increase in system complexity in implementing Massive MIMO radios are major hurdles. Integrating the analog signal chain with digital front end (DFE) devices in the radio and a substantial increase in signal processing compute power are needed to overcome these challenges. RFSoCs for 5G NR Massive MIMO A 5G NR Massive MIMO

implementation requires many active signal chains in the radio to connect to each antenna or a subset of antennas in the array. These active signal chains— which traditionally comprise data converters, filters, mixers, a power amplifier and a low noise amplifier— can lead to significant increases in power, form factor and costs. The large number of active signal chains in a Massive MIMO system and resulting increases in system power and footprint will make it difficult to realize commercially viable systems. The cost associated with moving data between the RF Front-Ends (RFFE) and the Digital Front End (DFE) is one of the key challenges that must be resolved for 5G—at the software, hardware, and system level.

Xilinx, for example, is addressing this challenge by replacing multiple ADCs and DACs along with other RF components on the board with direct RF-sampling data converters in its existing 16nm FinFET Multi- Processing SoC (MPSoC) family of products, which are designed and deployed for radio applications. This newly introduced SoC device family monolithically integrates RF sampling data converter technology, providing a wide- bandwidth platform for radio systems that is fully hardware- and software-programmable. Based on an ARM-class processing subsystem merged with FPGA programmable logic, the architecture features 12- bit, 4GSPS RF-sampling ADCs, and 14-bit, 6.4GSPS direct RF DACs, along with optimized digital down-

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