New-Tech Europe Magazine | Q1 2023

Powering the computational tsunami driven by AI, machine learning and big data

Ajith Jain, Vice President HPC Business Unit

Unleash new levels of compute performance with vertical power delivery As high-performance AI processor power levels continue to rise and core voltages decline with advanced process nodes, power system designers are challenged with managing ever increasing power delivery network (PDN) impedance voltage drops, voltage gradients across high-current, low-voltage processor power pins, transient performance specifications and power loss. In the case of clustered computing, where tightly packed arrays of processors are used to increase the speed and performance of machine learning, PDN complexity rises significantly as current delivery must be done vertically from underneath the array. Designing a PDN using the Vicor Factor i zed Power Archi tecture (FPA™) with current multipliers at

the point-of-load instead of legacy voltage averaging techniques, allows a significant step up in performance. This is enabled by the characteristics of point-of- load (PoL) power components: high current density, reduced component count and very importantly, flexibility in placement. PoL power components thus enable current to be delivered laterally and/or vertically to AI processor core(s) and memory rails, significantly minimizing PDN impedances. Understanding the peak current demands with today’s power delivery networks Modern day GPUs have tens of billions of transistors, a number which is growing with every new generation and product family and which is made possible by smaller process node geometries. Enhancements in

processor performance then follow with every new generation, but this comes at the price of exponentially increased power delivery demands. Figure 1 shows the dramatic increase in current requirements due to reduced transistor geometry and core voltages. Peak current demands of up to 2000A are now a typical requirement. In response to this power delivery challenge some xPU companies are evaluating multi-rail options where the main core power rails are split into five or more lower-current power inputs. The PDN for each of these rails must still deliver a high current while also needing individual tight regulation, which puts pressure on the density of the PDN and its physical location on the accelerator card. To further add to this complexity, the highly dynamic nature of machine learning workloads, result in very high di/dt transients lasting several

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