New-Tech Europe Magazine | Q1 2023

innovative architectures that can help unleash the full power of today’s high performance processors. Vicor power converter technology takes advantage of an unique Factorized Power Architecture that not only optimizes the power converter efficiency but also enables very low PDN losses associated with low voltage, high-current power delivery to the PoL (ASIC or a CPU or a GPU etc..) Lateral power delivery is an innovative technique where the two current multipliers (Vicor VTM™ modules) flank the north and south side or the east and west side of the processor. This technique is preferable for load currents of ~800A at 0.8V nominal with an associated 70µΩ of PDN at 100°C. Using these numbers, we can compute ~45W of power loss. A heat sink that covers both the 2.8mm tall current multipliers and the processor as shown in the picture would be a good thermal solution. This architecture is excellent for powering graphics accelerator cards (OAM or otherwise), networking ASICs and APUs used in hyperscale data centers or supercomputer cabinets. The Lateral-vertical power delivery technique is similar to lateral power delivery, but with this difference: only 70% of the power is delivered laterally using the current multipliers that flank the sides of the processor. An additional current multiplier on the bottom side of the processor will deliver the remaining 30% of the load current directly to the processor BGA. The hybrid of lateral and vertical achieves a reduction in PDN loss by almost a factor of four! This technique also frees board space to accommodate a second high current rail (aux) or HBM memory rails on the top side of the board around the processor.

Figure 3: Factorized Power Architecture (FPA™) factorizes the power into the dedicated functions of regulation and transformation. Both of these functions can be optimized and deployed individually to provide a high-density and high-efficiency solution.

Figure 4: Leveraging FPA, Vicor minimizes the “last inch” resistances with several patented solutions involving lateral power delivery (LPD) and vertical power delivery (VPD). All enable processors to achieve previously unattainable performance levels to support today’s exponentially growing HPC processing demands.

Vertical-lateral power delivery, on the other hand, takes advantage of pushing >50% of the load current through additional current multipliers on the bottom side of the processor. This technique enables a further 50% reduction in PDN loss compared to the lateral-vertical approach. A 1200A design can now realize a PDN resistance of a mere 10µΩ, resulting in fewer than 14.4W of power loss.

In this case, heat sinks can be placed on both the top and bottom sides of the load as space permits. This architecture is especially effective for applications that cannot afford power components on the top side of the board in order to accommodate high-speed signal routing from the periphery of the ASIC. Examples are CPO, NPO and networking / broadband communication devices.

22 l New-Tech Magazine Europe