New-Tech Europe Magazine | Q2 2021

Figure 6: Complete power solution. (Image source: Siemens EDA)

valleys, and hotspots in pre-silicon designs are challenges for quick and efficient power analysis. Add overcoming long turnaround times, high disk consumption, and bulky formats for waveform generation like fast signal database (FSDB) and value change dump (VCD). Accurate and realistic results can only be achieved running real-world OS and industry benchmarks, such as 3DMark, GFXBench, Geekbench, AnTuTu, which mandate a high-performance engine and an integrated validation flow. Hardware Emulation for Power Analysis A modern hardware emulator can generate an activity plot early in the design verification cycle by running real-world applications before register transfer level (RTL) code availability to quickly find where and when hotspots and valleys are happening. It can determine what is causing the spikes within hardware hierarchies and produce a hotspot map that shows which IP or blocks are power hogs.

Once the hardware emulation platform identifies time windows in the design hierarchies, it can generate detailed switching information within those windows to feed a power analysis tool. This is typically done by creating a flat-file streaming database (FSDB) or in Switching Activity Interchange Format (SAIF) files. A better approach would be via a direct API access from the emulator to the power tool and bypass the file generation for a faster and more efficient procedure. Once the power tool has the information, it can generate accurate power numbers to help to make changes to the RTL design to lower power consumption. After making the appropriate changes, a new verification cycle can validate the validity of those changes. Summary Market trends in data center networking, communication and 5G, autonomous driving, AI and ML, and storage positively impact the hardware-assisted verification landscape. Hardware-

assisted verification is a mandatory investment as chips get larger, more complex with more interfaces, and hardware and software code integration become critical early in the design side. No other verification tool can meet these challenges. About the Authors — Jean-Marie Brunet is senior director of product management and engineering for emulation and prototyping at Siemens EDA. He has served for more than 20 years in application engineering, marketing and management roles in the EDA industry, and has held IC design and design management positions at STMicrolectronics, Cadence, and Micron, among others. Lauro Rizzatti is a verification consultant and industry expert on hardware emulation. Previously, Rizzattiheldpositions inmanagement, product marketing, technical marketing, and engineering.

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