New-Tech Europe Magazine | Q2 2022

Cover Image credit: IMEC

Increasing the bit density requires new ways to address memory cells We believe there is a fundamental reason why it is challenging to scale further the bit densities of conventional solid-state memories (such as SRAM, DRAM, or 3D-NAND-Flash) cost-efficiently. In all these memories, the memory cells are organized in two- or three-dimensional arrays, at the cross-points of word- and bitlines. Each cell minimally consists of a storage element and an access device. The access device – usually a transistor or a diode – connects the storage element to at least two wires needed for selecting, reading, and writing the memory cell. The scaling challenge does not relate to the storage element itself (storage elements the size of a single molecule have already been demonstrated) but rather to the access device and its wiring. Cells are at least 2Fx2F (4F2) in size, with F the minimum feature size (for example, the wordline half-pitch) determined by the (expensive) lithography step used for patterning the wires. This configuration with one access device for each storage element makes it challenging to develop cost-efficient high- density solutions and store more than a few bits per cell (with 4-bit NAND-Flash cells currently being the maximum). A different strategy is pursued by HDD and tape storage technologies. Here, a significantly smaller number of read/write access devices connect to a larger un- patterned area that serves as the storage medium. This leads to higher densities and lower cost per bit than NAND-Flash. But also to slower, bulkier and energy- consuming solutions – as the reading heads must be mechanically positioned over a large area. Disruptive solutions couple a dense array of access devices to a volumetric storage medium By reconciling the best of both worlds, new approaches can be found for making

Figure 1: Indicative overview of today’s main memory technologies and their application domains, illustrating the trade-off between latency and productivity (also presented at IMW 2022).

ultrahigh-density storage devices at an affordable cost per bit that operate faster than, for example, tapes. Why not make a dense array of access devices that connect to a volumetric storage medium? Inspired by advances in life sciences, this storage medium could be a liquid containing ions, molecules, or (nano-)particles, which can be manipulated and moved in larger volumes to an access device that is part of a dense array. This approach would enable multi-bit operation, with significantly fewer access devices, wires, and lithography steps needed per bit. The high-density potential of this new approach has attracted interest from industry, and several liquid-based concepts are being investigated worldwide. Below, we propose two new liquid-based concepts with long-term potential for nearline storage, targeting (sub-)second access times. In this article, the focus is on their operating principle and first experimental results. More details were

presented at IMW 2022 [1], and work on the electrolithic memory was recently published in IEEE Transactions on Electron Devices [2]. Colloidal memory: manipulating nanoparticles A first liquid-based memory concept introduced by imec is referred to as the colloidal memory. It nicely shows how liquid (e.g., water) can be used as the volumetric storage medium and dissolved nanoparticles (the colloid) as carriers of the data symbols. The idea is to use a colloid of (at least) two types of nanoparticles (A and B) contained in a reservoir. This reservoir is attached to an array of capillaries, into which the nanoparticles can be inserted. Provided that the nanoparticles are only slightly smaller than the diameter of the capillaries, the sequence in which the particles (the bits) are entered into the capillaries can be preserved. It is

Figure 2: Three different types of addressing employed by memory technologies (also presented at IMW 2022).

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