New-Tech Europe Magazine | Q3 2021 | Digital Edition
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IoT Computers Components Computers Electro Optic & Camera Packaging & Production Motion Automotive New Products Programming Interface (API) that executes hardware instructions concurrently and simplifies the expression of complex hardware parallelism as compared to other HLS offerings. The SmartHLS tool requires up to 10 times fewer lines of code than an equivalent RTL design, with the resultant code being easier to read, understand, test, debug and verify. The tool also simplifies exploration of hardware microarchitecture design trade-offs and enables a developer’s pre-existing C++ software implementations to now be used with PolarFire FPGAs and FPGA SoCs.
Automotive
New Products
Electro Optic & Camera Packaging & Productio
Motion
Computers Communication
Motion
Communication
Motion Automotive
Smart High Level Synthesis (HLS) Tool Suite Enables C++ Based Algorithm Development Using Microchip’s PolarFire® FPGA Platform Enhances accessibility to PolarFire FPGAs for hardware acceleration in edge compute systems The need to combine performance with low power consumption in edge compute applications has driven demand for Field Programmable Gate Arrays (FPGAs) to be used as power-efficient accelerators while also providing flexibility and speeding time to market. However, a large majority of edge compute, computer vision and industrial control algorithms are developed natively in C++ by developers with little or no knowledge of underlying FPGA hardware. To enable this important development community, Microchip Technology Inc. (Nasdaq: MCHP) has added an HLS design workflow , called SmartHLS, to its PolarFire FPGA families that greatly enhances productivity and ease of design by allowing C++ algorithms to be directly translated to FPGA-optimized Register Transfer Level (RTL) code. “SmartHLS enhances our Libero® SoC design tool suite and makes the vast benefits of our award-winning mid- range PolarFire and PolarFire SoC platforms accessible to a diverse community of algorithm developers without them having to become FPGA hardware experts,” said Bruce Weyer, vice president of Microchip’s FPGA business unit. “Together with our VectorBlox™ Neural Network Software Development Kit these tools will greatly improve designers’ productivity in creating cutting-edge solutions using C/C++ based algorithms for applications such as embedded vision, machine learning, motor control and industrial automation using FPGA-based hardware accelerators.” Based on the open-source Eclipse integrateddevelopment environment, the SmartHLS design suite uses C++ software code to generate an HDL IP component for integration into Microchip’s Libero SmartDesign projects. This enables engineers to describe hardware behavior at a higher level of abstraction than is possible with traditional FPGA RTL tools. It further improves productivity while reducing development time through a multi-threading Application
Samtec Releases Family of AcceleRate® HP High-Performance Arrays Basis for new PICMG COM-HPC®Interconnect Solutions New Albany, IN: Samtec Inc., a privately held $800 MM global manufacturer of a broad line of electronic interconnect solutions, proudly announces the release of next-gen AcceleRate HP High-Performance Arrays. AcceleRate HP supports 112 Gbps PAM4 extreme performance in an ultra-micro footprint. AcceleRate HP High-Performance Arrays feature an open-pin-field array which maximizes grounding and routing flexibility. System architects can route high- performance differential-pairs, single-ended signals and high-current voltage rails via the same interconnect. Additionally, the 2.2 / 2.4 / 2.2 mm row pitch eases routing of differential signals. Crosstalk is improved with the increased space and the ability to add more ground vias around the differential signals. “Samtec’s new AcceleRate HP High-Performance Arrays set the standard for high-speed 112 Gbps PAM4 performance in a small form factor,” said Michael Boone, Product Manager, High-Speed Board-to-Board at Samtec,
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