New-Tech Europe | Oct 2016 | Special Edition For Electronica 2016

Figure 3: Leveraging metric-driven verification to provide a comprehensive functional safety regression analysis

safety assessment, and TCL for digital designs are the core requirements that have to be met today. The design and test teams start by identifying potential safety issues, along with the checking and error correction systems that can detect those faults. Those requirements are captured in a safety plan that augments the functional verification plan. These metric-driven verification plans monitor sets of metadata through both the functional and safety verification flows. For the functional flow, the metadata includes well-known coverage, test completion, and other metrics using conventional verification flows. While the functional safety flow adds a new technology for fault injection and detection, it needs to integrate seamlessly with the conventional flows for two

critical reasons - efficiency and tool confidence. Safety verification is a complex task so the teams need to reuse the environments already created in the conventional flow. Along these lines, achieving a TCL1 for the flow is dependent on both a well-known flow and redundant tooling. By fitting the fault injection and requirements tracing within the conventional flow, a TCL1 assessment for the flow is justified. As simulation provides a means for functional verification of systems, fault injection allows for functional safety assessment by simulating the behavior of the system under various error conditions by momentarily or permanently changing the values seen in a given simulation. Faults models include manufacturing-time stuck-at-0 and stuck-at-1 faults, as well as single event upset faults and transient faults that can occur

while the ICs are functioning in the system. Given this, fault simulation helps safety verification engineers cover a wide range of possible system malfunctions. While the TCL assessment is important, the efficiency of fitting in the conventional functional verification flow is equally important. Part of the safety assessment requires fault analysis at the gate level, which can be achieved with a fault injection using a well-proven gate-level simulator. However, the temporal faults can require longer simulations with more of the SoC context. This context can include both analog circuits and software, implying the need for mixed-signal and hardware-based verification. Moreover, the gate-level simulation can be exceedingly long, so safety engineers need to develop the safety verification at higher levels of

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