New-Tech Europe | Q3 2026 | Digital Edition

When the PCB Becomes Part of the Problem by New-Tech Magazine Group

How 224 Gbps PAM4 is pushing high-speed interconnects closer to the silicon Key Takeaways ■ The challenge: At 224 Gbps PAM4, PCB routing increasingly becomes a limiting factor in signal integrity. ■ The shift: Co-Packaged Connectivity moves the interconnect directly onto the package substrate, closer to the silicon. ■ The impact: Up to 3 dB lower channel loss, nearly 3× higher interconnect density, and low crosstalk.

At 224 Gbps PAM4, the challenge is no longer confined to generating and receiving faster signals. Increasingly, it is about what happens to those signals after they leave the silicon. Between an ASIC and its destination lies a complex electrical path that may include package substrates, solder balls, vias, PCB traces, connectors and cables. Each element introduces some combination of loss, reflections, impedance discontinuities, crosstalk and timing variation. As data rates increase, the margin available to absorb these effects becomes progressively smaller. This is the engineering problem at the centre of Samtec’s white paper, Achieving 224 Gbps PAM4: New Interconnect Methods to Ensure Signal Integrity. Rather than treating 224 Gbps as simply another step in connector performance, the paper examines a more fundamental question: how must the physical architecture of the high-speed channel change when conventional PCB-based interconnect paths begin consuming too much of the available signal budget? The answer increasingly points toward moving the interconnect closer to the silicon – and, in some cases, onto the package itself. 224 Gbps is more than another speed increase The transition from 112 Gbps PAM4 to 224 Gbps PAM4 may appear to be another doubling of data rate. Electrically,

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