New-Tech Europe | Q3 2026 | Digital Edition

however, the implications are much more demanding. As the data rate rises, channel impairments that could previously be accommodated become increasingly significant. Insertion loss, return loss, crosstalk and skew all consume a larger share of the available performance margin. At the same time, modern devices are increasing their I/O density. High-performance ASICs require large numbers of high-speed channels operating simultaneously, creating a difficult combination of signal density, power consumption and heat. Samtec identifies three challenges that become particularly important in this environment: signal integrity, power delivery and thermal management. These are increasingly interdependent. The physical space surrounding the ASIC must accommodate high-speed I/O while also providing sufficient power to the device and supporting the thermal solution required to remove the resulting heat. This makes the location and architecture of the interconnect a system-level design decision rather than simply a connector selection. Silicon is scaling faster than the PCB One of the most important observations in the Samtec paper concerns a widening technology gap. Semiconductor manufacturing has continued to scale aggressively, allowing increasing functionality and I/O density to be integrated into smaller areas. PCB technology has also advanced, but its fundamental feature sizes have not scaled at anything approaching the same rate. The result is a growing mismatch between the density available at the ASIC and the density that can practically be routed through a conventional printed circuit board. For high-speed system designers, this creates two related problems. More signals must be routed through limited PCB real estate, while the electrical performance of those routes becomes increasingly difficult to maintain as data rates rise.

The traditional architecture - in which signals leave the package through the BGA and are then routed through the PCB before reaching a connector - therefore begins to impose its own limitations. At 224 Gbps PAM4, the PCB is no longer simply the platform connecting the components. Parts of the PCB channel can become a significant contributor to the signal-integrity problem. Near-Chip shortened the channel - but did not eliminate it One response to increasing channel loss has been the Near Chip approach. Instead of routing high-speed signals across a substantial distance on the PCB, the connector is positioned close to the ASIC. The electrical signal is transferred to Twinax cable as early as possible, reducing the length of the PCB trace and therefore reducing the losses associated with board routing. This architecture has provided an effective solution for high speed systems, including 112 Gbps PAM4. But Near-Chip still leaves part of the conventional signal path intact. The signal must travel from the silicon through the package, BGA interface and PCB structures before reaching the connector. These transitions introduce losses, reflections and impedance discontinuities. At the same time, placing large numbers of high-speed connections around the ASIC consumes valuable board area that is also required for power delivery. At 224 Gbps, these compromises become increasingly difficult to ignore. Near-Chip can reduce the length of the electrical path. It Figure 1: CMOS feature scaling has progressed significantly faster than PCB feature scaling, creating a growing density gap between silicon and board-level interconnect technology. Credit: Samtec

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Samtec identifies three challenges that become particularly important in this environment: signal integrity, power delivery and thermal management.

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New-Tech Magazine Europe l 37