New-Tech Europe Magazine | June 2016

like Ethernet, and processors running at GHz rates, there is no concept of the exact clock cycle when a packet "should" arrive, so it lessens the need for perfect synchronization. An SoC is not really like that. The need for synchronization leads to two problems. It can consume a lot of the bandwidth of the cores just to maintain time. And if it is done wrong, there is a risk that causality will be violated. Some key features of RocketSim are: Reduces host memory footprint by over 5X Fast compilation of large designs Full debug visibility Billion+ gate capacity Four-state logic Compliant with Verilog IEEE 1364- 2001, 1364-2005, VHDL, System Verilog, OVM, VMM, and UVM PLI-compliant interface Runs alongside the test bench

could run large distributed simulations across many servers, but that was because we "cheated". We were not

truly running a single system, but a lot of separate systems connected by networks. When you have a network

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