New-Tech Europe | Aug 2019 | Digital Edition

interconnect granularity – the level of granularity at which the different parts of the system will be reconnected – and the technology heterogeneity. For example, if we want to reach a very fine interconnect granularity, we will not be able to reconnect a wide variety in technologies. After dis-integration, each of these sub-systems can then be designed and processed separately, with the most appropriate technology. Following this approach, we will move away from a longstanding guiding principle that has been used to make ever more advanced systems-on-chip: the universality of CMOS technology. So far, all the different functions on a chip (including, for example, logic, memory, I/O interfaces, power etc) were hooked onto one and the same CMOS technology platform. Scaling of that CMOS technology has enabled ever more performant systems. But as SoCs are becoming increasingly more heterogeneous, it will be more advantageous to use a different process technology – which could as well be multi-node variations of one technology – for the different needs of the sub-systems. Memory, for example, does not need to be process-compatible with logic. Or, think about sensors and other analog functionalities that do not really benefit from using ultimately scaled technologies. For these functions, simpler processes and more relaxed lithography can be used. With this approach, we expect to make even more progress in terms of power, performance, area and cost – offering new scaling opportunities for future electronic systems. Reintegration: 3D integration technologies to the rescue After disintegrating the SoC and optimizing the different sub-systems,

Figure 1: From DTCO to STCO

they need to be reintegrated in a smart way by using one of the available 3D integration technologies. Different 3D integration technologies can be applied at different levels of the interconnect hierarchy, spanning an exponential scale in interconnect density (i.e. the number of connections per mm2) – from the mm-scale to the nm-scale. This 3D interconnect technology landscape can be illustrated with the graph below. The graph represents the various 3D integration approaches with respect to the achievable 3D interconnect density and pitch. At the ‘coarser’ left side of the graph are the technologies that are typically being used if only a limited number of connections is needed between the system’s sub-components. Here, partitioning is done at package level, by stacking packages on top of each other. This system-in-a package (SiP) approach has been illustrated for the case of DRAM stacking. Coarse contact pitches in the order of 400µm can be achieved. As an alternative approach to SiP, multiple die can be integrated in a single package using passive interposers – known as 2.5D integration. This is for example being used for ‘chiplet’ style of manufacturing. Or, one of the many fan-out wafer-level packaging flavours can be applied, which are an attractive solution

for mobile applications such as smartphones – as they potentially enable cost-effective wide I/O die- to-die interconnects in small form factors. Many of these techniques use horizontal as well as vertical interconnections. Higher 3D interconnect densities can be achieved by using die-to- wafer stacking techniques, where finished dies are bonded on top of a fully processed wafer. Dies are interconnected using through-Si vias (TSVs) or microbumps. Imec’s goal is to bring these microbump pitches down, below 10µm. Next come wafer-to-wafer bonding techniques, enabling true 3D system-on-chips. These are packages in which partitions with varying functions and technologies are stacked heterogeneously, with interconnect pitches in the order of 1µm. Either hybrid wafer-to-wafer bonding or dielectric wafer-to-wafer bonding techniques can be applied. The highest interconnect density is realized so far by using sequential processes. Ultimately, transistors can be stacked on top of each other, achieving contact pitches as small as 100nm. The true value of these sequential processing is whenever a second layer needs to have a lithography precision of alignment with respect to the bottom layer. An interesting application that can

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