New-Tech Europe | Aug 2019 | Digital Edition

potentially benefit from this precise alignment, is ‘array under CMOS’ – involving splitting up the periphery from the array. This approach could be considered for applications such as imagers or selectors for memory. An unusual roadmap It is important to note that this 3D landscape should not be read like a timeline from left to right. There is no single packaging technology that can serve all needs. Instead, the different 3D integration options exist next to each other, and can even co-exist in one and the same system. And each option has its own roadmap, with interconnect densities and pitches improving in time. But the choice of what is the best 3D integration technology entirely depends on the application, and on the ‘traffic’ between each element that you partition. It is a collection of technologies that allow a system to be integrated into a much smaller form factor, with optimized performance and power, and at lower manufacturing cost – in support of STCO. Where logic and 3D meet: two STCO cases Various functions of a SoC (such as image sensors or memory components) have already been subject to partitioning and reintegration by using one of the available 3D integration technologies. But so far, the logic part of the system has mainly stayed out of this ‘3D picture’. Below, two cases illustrate how this has recently changed: the case of logic on memory, and the case of backside power delivery. Theywill showhow logic and 3D start to meet in the STCO framework, and how smart partitioning can provide a knob for further CMOS scaling.

Figure 2: The 3D technology integration landscape

Benefits of this approach are a potential reduction in die area, and an obvious reduction in footprint. It also allows functional memory (e.g. the level-2 cache) to be positioned in close proximity to the logic it serves, with the average line length being the vertical spacing between the two components. This results in increased performance (interconnect bandwidth) at reduced power consumption. Backside power delivery The goal of a power delivery network is to provide power and reference voltage to the active devices on the die. This network is essentially a network of interconnects that is completely separate from the signal network. Traditionally, both the signal and power networks are processed in

In both cases, we consider three key functions of the SoC: logic core, cache memory and storage, and power delivery. Logic on memory In traditional systems, a memory array is placed next to the logic core that it supports. This gives an average interconnect line length that depends on both the spacing between the two devices and the bump pitch on the individual die. Alternatively, functional partitioning and wafer-to-wafer bonding techniques can be used to stack the memory vertically on top of the logic component. The memory can be manufactured in a memory-optimized process on one wafer, and core logic can be manufactured on another.

Figure 3: Principle of functional backside power delivery network using nano-TSV to contact buried power rails through ultra-thin Si device layers.

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