New-Tech Europe Magazine | July 2017

Taking the Risk Out of SW-Driven Networking SoCs

Ron Squiers

The massive adoption of software- driven networking (SDN) architectures has been driven by the upsurge of new markets such as cloud computing, big datacenters, and mobile. In turn, SDN dramatically pushes design complexity, size, and port counts to new heights, posing several challenges to stressed-out design teams developing one of these monster SoCs. These challenges cannot be addressed by traditional software- based simulation tools, nor by formal tools. In the billion-gate arena, only hardware-driven verification engines can accomplish these challenging tasks, meet a tight schedule and avoid fatal delays that may wipe out potential revenues in the fast moving networking market. Among the hardware-based verification engines, hardware

emulation has emerged as the best tool for pre-silicon verification. A modern emulator provides virtually unlimited capacity to emulate the largest designs, offers total design visibility and access/control without instrumentation/compilation and supports high throughput, along with fast, predictable compile and bring-up time. It can accommodate multiple concurrent users with optimum utilization of resources. It can be deployed in several modes of operation to perform a multitude of verification tasks. When it comes to verifying a networking SoC design with many ports, design teams are moving from a traditional in-circuit emulation (ICE) setup to a virtual test environment, eliminating any hardware and, with that, all hardware dependencies, including noise, power, cables,

reliability and associated costs. Virtual devices can be built before availability of actual hardware by using a combination of software and synthesizable hardware models, which facilitates easy reconfigured through this software. They run at emulation speed, support multi- users and multi projects, are accessed remotely and deployed in datacenters. The virtual mode, however, requires the creation of a virtual test environment, a non-trivial task. In this regard, Mentor Graphics took the lead and developed a comprehensive and sophisticated virtual environment, called VirtuaLAB, to support pre-silicon testing of application-specific SoC designs. For networking designs, VirtuaLAB includes an Ethernet Packet Generator and Monitor

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