New-Tech Europe Magazine | July 2017

(EPGM) that generates, transmits and monitors Ethernet packets to/ from the design under test (DUT). It has the ability to configure25GMII, 50GMII, 200GMII, 400GMII. Each VirtuaLAB supports up to 32 ports. Multiple VirtuaLAB systems can be assembled to expand the port count to greater than 1000. Figure 3 compares an ICE setup versus an equivalent VirtuaLAB for testing a 128-port Ethernet switch. As powerful as a VirtuaLAB for pre- silicon verification can be, when applied to post-silicon testing of engineering samples in the lab, its effectiveness is encumbered. Instead, the methodology for testing networking engineering samples in the lab is through the use of dedicated hardware networking testers. Under this scenario, the verification landscape shows two gaps. The first is a gap between simulation and emulation. The second gap is between pre-silicon verification, based on hardware emulation and VirtuaLAB performed in a design center, and post-silicon testing performed by specialized testers in a lab. Once more taking the lead, Mentor Graphics spearheaded an initiative to fill the gap between the emulation environment and the lab. It entered into an agreement with IXIA, worldwide leading provider of comprehensive solutions for testing of network equipment and network applications. IXIA products cover the entire spectrum of networking testing needs, from performance, to functional, to security and conformance testing, including physical testers and virtual testers. Continuing to expand the catalog of Veloce Emulation Platform Apps, Mentor and IXIA jointly developed an integration between IXIA’s IxNetwork® Virtual Edition (VE) test

Figure 1: Complexity and gate counts have increased with new SDN applications

Figure 2: A block diagram represents the Mentor/IXIA networking integrated solution

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