New-Tech Europe Magazine | Q2 2022

Q2 2022

16 New ABB study on industrial transformation unveils critical relationship between digitalization and sustainability 18 Level-Setting DAC Calibration for ATE Pin Electronics 22 Exploring liquid- based memories for ultrahigh-density storage applications

26 Making Robots More Efficient with Adaptive Computing

MEET TODAY’S PRODUCT LAUNCH CHALLENGES Arena PLM helps get your products to market quicker! With increasing product complexity and global product teams, you need a way to simplify and streamline high-tech product development and launch processes. Creating, sharing, reviewing, and approving product designs across dispersed internal teams and supply chain partners is critical to your success. Arena’s cloud-based Product Lifecycle Management (PLM) meets the challenge by bringing your entire product record into a single source of truth to connect people, product information, and processes anytime and anywhere. Join over 1,300 global companies using Arena to: • Streamline NPDI processes and speed product launches • Ensure accuracy with a central product record (mechanical, electrical, and software)

• Eliminate build errors, shortages, scrap, and reword • Reduce operational costs and increase profitability • Speed engineering change cycle time

New-Tech Exhibition Visit us at booth 57A

• Simplify regulatory compliance Get in touch at arenasolutions.com

More new products in stock

Order

confidence with

mouser.com/new

NEXT GENERATION CONNECTIVITY FROM SILICON-TO-SILICON

Samtec’s industry-leading signal integrity expertise, full system optimization strategies, and innovative products and technologies provide a path to 224 Gbps performance and beyond.

Samtec Israel 21 Bar-Kochva St. • Concord Tower • B’nei Brak, Israel 51260 Tel: +972 3 7526600 • Fax: +972 3 7526690 E-mail: israel@samtec.com

www.samtec.com

King of Coax Connection.

© eiCan

#KINGOFCOAX

Coaxial Connectors The SMA connector is designed for a frequency range of DC to 18 GHz at 50 Ω impedance. With its threaded-type coupling mechanism, it is perfect for securing your connection in intensive vibration environments.

n Standard interface in accordance with MIL-STD-348 n Precise CNC machining with up to 0.003 mm tolerance n Center contact captivation n Resistant to severe conditions for up to 48 hours

For further information, please visit: www.we-online.com/coax

High Reliability Interconnection Powell Electronics in Europe Connectors, cables, value-added assembly

Quell Glenair Harwin Amphenol Aerospace AB Connectors Lemo Conesys and more…

WHAT IF WE COULD CREATE MORE BY WASTING LESS? By 2050, global energy demand is projected to rise by over 60%. ADI’s expertise in power management has enabled breakthroughs like energy harvesting and robotic miniaturization. Which means we can make progress, while making less waste.

Analog Devices. Where what if becomes what is. See What If: analog.com/WhatIf

Q2 2022

About New-Tech Magazines Group Read To Lead ‘New-Tech Magazines’ A world leader in publishing high-tech and electronics, producing top quality publications read by tens of thousands professionals from all over the world especially from Europe, innovative electronics, IoT, microwave, homeland security, aerospace, automotive and technological industries. Our specialized target audiences prefer New-Tech Europe because they know that our publications are a reliable source of the latest information in their respective fields. Our multidimensional editorials, news items, interviews and feature articles provide them with a full, well-rounded picture of the markets in which they operate - an essential asset for every technological leader striving to stay ahead, make the right decisions, and generate the next global innovation. Moreover, as an attractive platform for advertisers from around the world, New-Tech Europe has become a hub for bustling international commercial activity. Here, through ads and other promotional materials, Israeli readers obtain crucial information about developers and manufacturers worldwide, finding the tools, instruments, systems and components they need to facilitate their innovative endeavors. Targeting the needs of both the global and european industries and global advertisers, New-Tech Magazines Group constantly expands and upgrades its services. Over the years, the company has been able to formulate a remarkably effective, multi-medium mix of offerings, combining magazine publications with useful online activities, newsletters and special events and exhibitions.

Editor: Tomer Gur-Arie COO & CFO: Liat Gur-Arie Journalist: Amir Bar-Shalom Technical journalist:

Arik Weinstein Graphic Design: Hadas Vidmayer Concept design: Maya Cohen

mayaco@gmail.com Technical counselor: Arik Weinstein Sales and advertising:

sales@new-techmagazine.com Account Manager: Yuval Gur-Arie Account Manager: Sivan Bekerman Project Manager/Events: Shiri Abdi Project Manager/Events: Yaara shahaf Data system: Liat Tsarfati Editorial coordinator: Lihi Levi Operation Manager: Sivan Bekerman Mail: Office:

info@new-techmagazine.com Publisher :

NEW-TECH MAGAZINE GROUP LTD

www. new- t echeurope . com

8 l New-Tech Magazine Europe

Contents

10 LATEST NEWS 16 New ABB study on industrial transformation unveils critical relationship between digitalization and sustainability 18 Level-Setting DAC Calibration for ATE Pin Electronics 22 Exploring liquid-based memories for ultrahigh-density storage applications 26 Making Robots More Efficient with Adaptive Computing 30 The world runs on semiconductors

16

18

34 OUT OF THE BOX 36 NEW PRODUCTS 46 INDEX

22

26

www. new- t echeurope . com

New-Tech Magazine Europe l 9

Latest News

NSITEXE Selects ImperasDV for Automotive Quality RISC-V Processor Functional Design Verification

Imperas RISC-V Reference Model, Test suites and VerificationIPforadvanced ‘ l o c k - s t e p - c omp a r e ’ Processor Verification including Asynchronous events and Coverage Analysis.

hart, and custom extensions. In addition, the freedom of the open standard ISA of RISC-V is enabling advanced processor technology in many new application areas with developers exploring techniques such as superscalar, out-of-order execution, multi- threading, heterogeneous multi-core and processor arrays plus other new and creative approaches for

Imperas Software Ltd., the leader in RISC-V simulation solutions, announced that NSITEXE, Inc., a group company of

Photo credit: NSITEXE

the next generation of domain specific devices. ImperasDV complements the verification tasks for development teams at the forefront of processor exploration. “The flexibility of the RISC-V ISA coupled with the performance of vector extensions is an ideal starting point for AI accelerators for automotive applications,” said Hideki Sugimoto, CTO of NSITEXE, Inc., a group company of DENSO Corporation. “To address the verification requirement for our next generation of processors, we have developed an optimized verification flow with ImperasDV that our design team set up with detailed configuration options to deliver on their comprehensive verification plans that provides the industry leading quality our customers expect.” “The open ISA of RISC-V is enabling a new wave of processor design innovation across the spectrum of compute requirements in almost all market segments,” said Nobuyuki Ueyama, President of eSOL TRINITY Co., Ltd. “High quality processor verification is not a simple task, but the ease of use and configurable approach with RVVI offered by ImperasDV enables the eSOL TRINITY team to support the expert design teams at NSITEXE and other leading adopters of RISC-V in Japan.” “The open standard ISA of RISC-V is enabling a fundamental shift in processor development, with developers able to explore and innovate solutions with optimized solutions for targeted applications,” said Simon Davidmann, CEO at Imperas Software Ltd. “The flexibility of RISC-V on the design side has a direct impact on the verification

the DENSO Corporation that develops and sells high- performance semiconductor IP for automotive applications, has selected ImperasDV™ for advanced RISC-V processor hardware design verification. This expands and extends the use of Imperas simulation technology, models, verification IP and tools by NSITEXE for the next generation of 64bit RISC-V based designs featuring vector accelerators for AI (Artificial Intelligence) automotive applications with verification leading to the level required to achieve ISO 26262 ASIL D. RISC-V is an open standard ISA (Instruction Set Architecture) that allows processor developers to optimize the configuration with both standard extensions and custom instructions. The recently ratified RISC-V Vector Extensions support the compute requirements for hardware accelerators for applications involving linear algebra, which is well suited for the emerging AI algorithms and workloads in advanced automotive applications. ImperasDV is the integrated solution for RISC-V processor verification that provides an adaptable frameworkbasedontheopenstandardRVVI (RISC-V Verification Interface) that supports the core RTL verification with the Imperas reference model in a ‘lock-step-compare’ methodology in addition to test suites and other verification IP. ImperasDV covers the verification tasks for implementations that range from basic controllers through to advanced designs featuring vector extensions, privileged mode security protections, multi-

10 l New-Tech Magazine Europe

Latest News task, and since the value-added features are central to the development, we developed ImperasDV to be adaptable for all implementations to allows our customers and users to verify state-of-the-art designs independently. NSITEXE are pioneers in developing advanced RISC-V vector accelerators for AI, and we are pleased to see the Imperas technology and ImperasDV supporting the quality requirements for automotive applications.” Availability ImperasDV is available now, with more details available at Imperas.com/ImperasDV. The ImperasDV RISC-V processor verification technology is already in active use with many leading customers, some of which have working silicon prototypes and are now working on 2nd generation designs. These customers, partners and users span the breadth of RISC-V adopters from open source to commercial; research to industrial; microcontrollers to high performance computing. A select sample of these include – Codasip, EM Microelectronics (Swatch), NSITEXE (Denso), Nvidia Networking (Mellanox), OpenHW Group, MIPS Technology, Seagate Technology,

Silicon Labs, and Valtrix Systems, plus many others yet to be made public. The open standard RVVI (RISC-V Verification Interface) provides the essential guidelines for the infrastructure around the processor testbench that supports the growing ecosystem of Verification IP for RISC-V processor verification. The new RVVI open standard and methodology, is based on an open specification (https://github.com/riscv- verification/RVVI) and can be adapted to any configuration permitted within the RISC-V specifications. In adopting the RVVI standard, developers can leverage all the common components off the shelf and explore additional options with reusable Verification IP across projects. The free riscvOVPsimPlus package, including the Imperas RISC-V Reference Model, sample test suites and instruction coverage analysis, including updates for the latest RISC-V ratified specifications is also available on OVPworld at www. ovpworld.org/riscvOVPsimPlus.

Lanner Electronics Launches Falcon H8 PCIe AI Accelerator Card, Powered by Hailo-8™AI Processors

the edge, including intelligent transport systems (ITS), smart cities, smart retail, and Industry 4.0. The Falcon H8 is one of the most cost-efficient PCIe AI accelerator cards on the market, with a low power consumption and record high of up to 156 tera operations per second (TOPS) to allow high- end deep learning applications on edge servers. Lanner’s Falcon H8 modular, PCIe FHHL form factor provides a compact and easily deployable

Lanner Electronics & Hailo collaborate on one of the most cost-efficient PCIe accelerator cards on the market, with record high tera operations per second (TOPS), enabling high-end deep learning applications on edge servers Lanner Electronics, a global leader in the design and manufacturing of intelligent edge computing appliances, announced its first Hailo-8™AI- powered PCIe accelerator card,

NXP Brings Dolby Atmos® and DTS:X® to the Masses with its New Immersiv3D Audio Solution credit: Lanner Electronics

solution for engineers looking to offload CPU loading for low-latency deep learning inference. With high-density AI processors, the Falcon H8 accommodates 4, 5, or 6 Hailo-8™ AI processors, offering a modular, cost-

the Falcon H8. Lanner Electronics collaborated with leading AI (Artificial Intelligence) chipmaker Hailo to design the Falcon H8, enabling scalable and powerful intelligent video analytics applications for multiple industries operating at

New-Tech Magazine Europe l 11

Latest News

Arrow Inc. (NYSE:ARW) today announced Sean J. Kerins as president and chief executive officer (CEO), effective June 1, 2022, succeeding Michael J. Long who, effective June 1, 2022, will become executive chairman of the Arrow board of directors. Additionally, Arrow Electronics, Inc. announced Kerins will join the Arrow board of directors effective following the Annual Meeting of Shareholders on May 11, 2022. Kerins, a nearly 15-year veteran of Arrow, served as chief operating officer since December 2020. Prior to that he served as president of Arrow’s global enterprise computing solutions business since 2014, and previously president of the North American region for that business. Before joining Arrow in 2007, Kerins spent ten years at EMC in sales and Electronics, effective Edge AI solution with high processing capabilities and power efficiency. Through a standard PCIe interface, the Falcon H8 AI Accelerator Card enables legacy devices such as NVRs, Edge AI boxes, Industrial PCs and robots to run video-intensive, mission-critical Edge AI applications such as video analytics, traffic management, access control, and beyond. The Falcon H8 delivers unprecedented inference processing of over 15,000 Frames Per Second (FPS) for MobileNet-v2 and 8,000 FPS for ResNet-50. Its performance is up to 4x more cost effective (TOPS/$) and 2x more power efficient (TOPS/W) compared to leading GPU-based solutions. “Optimized for AI functionality, performance, and ease of deployment, Lanner is pleased to partner with Hailo to design a next-gen AI accelerator card that brings top- performing AI computing to the edge of industrial IoT,” said Jeans Tseng, CTO of Lanner Electronics. “Our expertise in creating high-density hardware platforms, combined with Hailo’s state-of-the-art neural chip and software framework,

provides service providers and system integrators a best- in-class AI accelerator that enables running deep learning applications most efficiently with the lowest total cost of ownership.” “The integration of Lanner’s Falcon H8 and the Hailo-8 provides unmatched AI performance at the edge. This joint solution is more powerful, scalable, and cost-effective than other solutions available on the market today,” said Orr Danon, CEO and Co-Founder of Hailo. “Our collaboration with Lanner will better power edge devices across industries, including transportation, smart cities, smart retail, industrial IoT, and more.” Lanner Electronics and Hailo first announced their collaboration in 2021, launching groundbreaking AI inference solutions for real-time computer vision at the edge. Several Tier-1 customers have since adopted the companies’ groundbreaking platforms.

Arrow Electronics, Inc. Names Sean J. Kerins President and Chief Executive Officer Succeeding Michael J. LongWho Will Become Executive Chairman of the Board of Directors

professional services roles, as well as progressively senior roles at Coopers & Lybrand Consulting, also serving as an industrial engineer at General Motors. Kerins holds a bachelor’s degree in engineering

from Syracuse University and a Master of Business Administration degree from Northwestern

Main photo credit: Arrow Electronics

University’s Kellogg School of Management. “I am honored to lead this company into the future,” said Kerins. “It truly has been a privilege to work with Mike and the talented Arrow team for the past almost 15 years. I look forward to our continued focus on driving profitable growth and value creation for our shareholders, suppliers, customers, and employees.” “Sean’s leadership and proven track record at Arrow

12 l New-Tech Magazine Europe

Latest News

our shareholders,” said Perry. “It has been an honor to work with the exceptional team at Arrow over the course of my career,” said Long. “Talent and succession management are central to our strategy. After a thoughtful and multi-year succession process, I am delighted Sean has been named president and CEO. I am confident in his leadership to guide Arrow into the future, and I look forward to continuing to serve on the Arrow board of directors.”

make him the ideal executive to succeed Mike Long,” said Barry W. Perry, lead independent director of the Arrow board of directors. “Our commitment to multi- year succession planning provides continuity for our shareholders, customers, suppliers, and employees.” “Further, we are pleased Mike will become executive chairman of the Arrow board of directors ensuring his decades-long leadership and mentorship at Arrow and extraordinary performance as chairman, president and CEO continue to inform Arrow’s strategy for the benefit of

BittWare Announces Partner Program to De-Risk Innovation and Reduce Time-to-Market for FPGA-Based Solutions

Pairing new IP and solutions with BittWare’s compute, network, storage and sensor processing accelerator products reduces risk while accelerating time to market

market and technology hurdles by facilitating an ecosystem of FPGA-based enablement IP and full solutions that utilize BittWare’s proven FPGA accelerator technology.

“BittWare is taking a leadership role in developing a partner program that empowers FPGA designers to access a robust ecosystem of proven IP cores, tools,

Partners poised to leverage FPGA strengths for performance-intensive apps, including ML/AI, 5G, database acceleration, test & measurement and security Approved supplier status for combined solution at leading OEMs globally to simplify and de-risk the purchase of third-party IP and solutions BittWare, a Molex company, a leading supplier of enterprise-class accelerators for edge and cloud-computing applications, today introduced a new partner program designed to simplify and streamline customer deployments of high-performance, data-intensive applications. As Field Programmable Gate Arrays (FPGAs) increase in size, complexity and performance, organizations grapple with time-consuming, costly and resource-intensive processes to develop the customized Intellectual Property (IP) and board-level capabilities needed for specific applications. The new BittWare Partner Program removes major time-to-

credit: BittWare

frameworks and solutions from a centralized source,” said Craig Petrie, VP, Sales and Marketing of BittWare. “In doing so, we are uniquely positioned to close critical gaps in the FPGA design process while reducing risk and accelerating commercialization of innovative, high-performance applications.” Ecosystem of Collaborators & Innovators The new partner program aligns powerful solutions from industry-leading and emerging IP providers with BittWare’s compute, network, storage and sensor processing accelerator technologies. In addition to achieving faster out-of-the-box functionality, the ability to combine critical components of the FPGA design process reduces engineering and programming requirements, enabling customers to focus in- demand resources on developing unique capabilities.

New-Tech Magazine Europe l 13

Latest News

Moreover, customers benefit from the opportunity to collaborate much earlier in the design process to meet the varying demands of powerful next-generation applications, such as artificial intelligence, machine learning inference, database acceleration, computational storage, 5G, test and measurement and security. The inaugural list of ten partners includes well-established leaders and innovative newcomers focused on solving tough challenges in the following categories: Compute: Intel: BittWare leverages the Intel Agilex FPGA technology and oneAPI toolkits to simplify development of High-Performance Computing (HPC) applications EdgeCortix: an edge AI-focused fabless semiconductor company with a software-first approach, focused on delivering class-leading efficiency and low-latency for AI Inference Megh Computing: provider of real-time, AI-based video analytics solutions Network: Atomic Rules: provider of mission-critical, enterprise- grade IP cores and solutions from the datacenter to the edge Enyx: developer of ultra-low-latency, FPGA-enabled technologies and solutions for the financial, telecom and HPC industries Grovf: developer of application acceleration and network offload solutions using FPGA chips Siama Systems: provider of Ethernet/IP network infrastructure test solutions for the 5G RAN, MEC and data centers Xiphera: developer of secure and efficient cryptographic IP cores, designed directly for FPGAs Storage: Eideticom: developer of computational storage solutions for cloud, HPC and enterprise data centers IntelliProp: provider of IP cores, ASIC design and verification services for the storage industry Supporting Partner Quotes: “We are excited to bring the power of EdgeCortix’s Dynamic Neural Accelerator IP to Intel Agilex FPGAs through

the new BittWare Partner Program,” said Sakyasingha Dasgupta, Founder and CEO of EdgeCortix. “It’s a game changer on several levels in the AI acceleration market. Together with BittWare, we are delivering a complete solution, from servers to edge boxes, which can be used as ‘drop-in’ replacements for CPUs or GPUs, while improving the performance. From an end-customer perspective, the solutions are easily accessible to software engineers, using standard frameworks like PyTorch, TensorFlow and ONNX. While, from a performance perspective, our solutions deliver significantly lower inference latency on high- resolution streaming data with up to a 7X performance advantage compared to competing FPGA-based offerings.” “Megh is proud to be part of BittWare’s FPGA partner program,” said Prabhat K. Gupta, CEO of Megh Computing. “Megh provides an AI-based, fully customizable, cross- platform Video Analytics Solution (VAS). The VAS Suite offering supports various use cases to reduce security risks and improve operational efficiencies for smart buildings and smart factories. This offering benefits from the acceleration provided by BittWare’s cards with Intel FPGAs to deliver the highest performance for the lowest TCO.” “IntelliProp is excited to be a part of the BittWare Partner Program to bring value to the storage and memory market by enabling quick-to-market, production-ready IP and reference designs targeting robust BittWare hardware platforms,” said Hiren Patel, CEO of IntelliProp. “We feel the IntelliProp NVMe bridge platforms will bring great benefit to our customers who are looking to implement compression, encryption, or other inline computational functions to solid state drive (SSD).” Members of the new BittWare Partner Program have chosen the company’s enterprise-class accelerators as one of their preferred platforms for the deployment of advanced compute, network and storage solutions. These significant industry collaborations yield a multitude of benefits, including the ability to decrease development time from up to a year or more to three months or less, as reported by our partner organizations. Additionally, customers gain the peace of mind that performance, quality, reliability and interoperability have been validated. For more details on the BittWare Partner Program, please visit the BittWare website.

14 l New-Tech Magazine Europe

Latest News Imec and Buhler Leybold enable high-throughput manufacturing of filter-on-chip CMOS sensors with unmatched precision

Buhler Leybold Optics, a supplier of cutting-edge thin-film vacuum coaters and imec, a world-leading research and innovation center in nanoelectronics, announce that they have qualified Buhler’s HELIOS 800 tool to meet the stringent standards of the semiconductor industry and developed high performance filters for optical image

Imec and Buhler Leybold Optics engaged in a joint development project, installing a HELIOS 800 Gen II in imec’s 200mm clean room. Within the framework of their collaboration, the HELIOS 800 Gen II was successfully upgraded to meet the extremely high standards of semiconductor manufacturing, with respect to contamination and particles levels.

Main photo: The HELIOS800 GenII in imec’s 200mm cleanroom

sensors. The enhanced tool opens up many new applications that require a precise deposition of high- quality optical stacks at high manufacturing speed. The development is going to lead to a new generation of high-resolution low-cost hyperspectral imaging sensors. The production of high-resolution low-cost filter-on-chip CMOS detectors for hyperspectral imaging sensors (HSI) for the visible (VIS) and the short-wave infrared (SWIR) range places high demands on thin-film deposition tools. A superior optical performance and low defect levels of the interference filters, combined with maximized wafer throughputs is needed. However, state-of-the-art deposition tools in semiconductor foundries lack a sufficient coating uniformity and optical performance as well as an in-situ thickness control. In the absence of such in-situ layer thickness control, the optical properties of filter stacks with up to hundreds of layers would need to be measured after the deposition of each individual layer. This dramatically reduces wafer throughput, making layer thickness corrections almost impossible. An in-situ optical monitoring system in the HELIOS 800 Gen II sputter coater allows complex filter coatings with excellent precision in a single production step, in which batches of multiple wafers are processed. Combined with the outstanding single layer quality in terms of thickness uniformity and optical properties as well as its low defect levels, the HELIOS 800 Gen II can pave the way to the next generation of highly resolved HSI sensors.

As a result, filters are now within the capabilities to be manufactured at high volume. Currently, imec and Buhler are collaborating to further upgrade the HELIOS 800 Gen II to enable numerous other applications and to enable processing of more complex optical filter architectures, such as photonics devices. This know-how will also be transferred to Buhler’s new sputter coater HELIOS 1200, capable to process 300mm wafers. The joint development project has been extended over the coming years, to enable the next generation of sensors and chips. Andy Lambrechts, program director imaging technologies at imec: “Collaborating with Buhler has been of great value to imec. It enabled us to increase the quality of our hyperspectral detectors by decreasing the tolerances on the filters and facilitating more complex filter architectures. The system is available to partners for R&D projects with the support of imec in testing and qualification.” Stephan Mingels, team leader M2M development at Buhler:: “Imec enabled Buhler to gain additional experience in front- end semiconductor processing environments. Moreover, the access to imec’s facility including high-end metrology equipment, has been crucial to optimize the performance of the HELIOS 800 Gen II.”

New-Tech Magazine Europe l 15

New ABB study on industrial transformation unveils critical relationship between digitalization and sustainability New-Tech Magazine Group LTD.

“Billions of better decisions” highlights the role of Industrial IoT solutions in reaching sustainability goals while empowering the industrial workforce International survey of 765 decision- makers reveals that while 96 percent believe digitalization is “essential to sustainability,” just 35 percent have implemented Industrial IoT solutions at scale 72 percent of companies are increasing investment in Industrial IoT specifically to address sustainability aims ABB released the f indings of a new global study1 of international business and technology leaders on industrial transformation, looking at the intersection of digitalization and sustainability. The study, “Billions of bet ter dec i s i ons: indust r i a l transformation’s new imperative,” examines the current take-up of the Industrial Internet of Things (IoT) and its potential for improving energy efficiency, lowering greenhouse gas

emissions and driving change. The goal of the new ABB research is to spur discussion within industry regarding opportunities to leverage the Industrial IoT and empower companies and workers to make better decisions that can benefit both sustainability and the bottom line. “Sustainability goals more and more are a crucial driver of business value and company reputation, and Industrial IoT solutions are playing an increasingly important role in helping enterprises achieve safe, smart and sustainable operations,” said Peter Terwiesch, President of ABB’s Process Automation business area. “Unlocking insights hidden in operational data holds the key to enabling literally billions of better decisions throughout industry and acting upon them, with significant gains in productivity, reduced energy consumption and lower environmental impact.” The study, commissioned by ABB,

found that an organization’s “future competitiveness” is the single greatest factor – cited by 46 percent of respondents – in industrial companies’ increased focus on sustainability. Yet while 96 percent of global decision- makers view digitalization as “essential to sustainability,” only 35 percent of surveyed firms have implemented Industrial IoT solutions at scale. This gap shows that while many of today’s industrial leaders recognize the important relationship between digitalization and sustainability, the adoption of relevant digital solutions to enable better decisions and achieve sustainability goals needs to accelerate in sectors like manufacturing, energy, buildings and transport. Further key learnings from the study 71 percent of respondents reported greater priority given to sustainability

16 l New-Tech Magazine Europe

ABB innovations for sustainability ABB is committed to leading with technology to enable a low-carbon society and a more sustainable world. Over the past two years, ABB has reduced greenhouse gas emissions from its own operations by more than 25 percent. As part of its Sustainability strategy 2030, ABB expects to be fully carbon neutral by decade’s end and to support its global customers in reducing their annual CO2 emissions by at least 100 megatons by 2030, the equivalent of removing 30 million combustion cars from the roads each year. ABB’s investments in digital capabilities are core to this commitment. With more than 70 percent of ABB’s R&D resources dedicated to digital and software innovations, and a robust ecosystem of digi tal partners, including Microsoft, IBM and Ericsson, the company has established a leading presence in Industrial IoT. The ABB AbilityTM portfolio of digital solutions enables a host of industrial use cases to power improvements in energy eff iciency, resource conservation and circularity, including condition monitoring, asset health and management, predictive maintenance, energy management, simulation and virtual commissioning, remote support and collaborative operations. Examples of ABB’s more than 170 Industrial IoT solutions include ABB AbilityTM Genix industrial analytics and AI suite; ABB AbilityTM Energy and Asset Manager; ABB AbilityTM Condition Monitoring for Powertrains; and ABB AbilityTM Connected Services for industrial robots. To learn more about ABB Ability, visit: https://global. abb/topic/ability/en To continue the conversation on this important topic, ABB will host an industry webinar on Wednesday, March 2, focused on the convergence

of digitalization and sustainability, and how the Industrial IoT and related technologies can help save energy, conserve resources, and improve safety for personnel and communities. Leading technology journalist and climate investor Molly Wood will moderate this virtual panel discussion featuring senior executives, best-selling authors and other thought leaders to explore this convergence and how industrial organizations can empower better, more sustainable decision-making throughout the enterprise. ABB (ABBN: SIX Swiss Ex) is a leading global technology company that energizes the transformation of society and industry to achieve a more productive, sustainable future. By connecting software to its electrification, robotics, automation and motion portfolio, ABB pushes the boundaries of technology to drive performance to new levels. With a history of excellence stretching back more than 130 years, ABB’s success is driven by about 105,000 talented employees in over 100 countries. www.abb.com [1] ABB “Billions of Better Decision” survey, August 2021. Conducted by California-based market research firm IntelliSurvey, the survey of 765 decision-makers in large and medium- sized businesses was fielded online in local languages in China, Italy, Germany, Sweden, Switzerland, the United Kingdom and the United States. Respondents were drawn from 12 industrial segments, including energy, manufacturing and transportation. The survey data col lected was supplemented by in-depth qualitative interviews wi th subject matter experts in digital transformation and sustainability.

objectives as a result of the pandemic 72 percent said they are “somewhat” or “significantly” increasing spending on Industrial IoT due to sustainability 94 percent of respondents agreed the Industrial IoT “enables better decisions, improving overall sustainability” 57 percent of respondents indicated the Industrial IoT has had a “significant posi t ive effect” on operat ional decision-making P e r c e i v e d c y b e r s e c u r i t y vulnerabilities are the #1 barrier to improving sustainability through the Industrial IoT Win-win scenarios with the Industrial IoT With 63 percent of executives surveyed strongly agreeing that sustainability is good for their company’s bottom line, and 58 percent also strongly agreeing it delivers immediate business value, it’s clear that sustainability and traditional priorities of Industry 4.0 efforts – speed, innovation, productivity, efficiency, customer-centricity – are increasingly intertwined, opening up win-win scenarios for companies looking to drive efficiency and productivity while making strides on climate change. “The International Energy Agency2 estimates that industry accounts for more than 40 percent of global greenhouse gas emissions today,” said Terwiesch. “If we are to reach climate objectives such as the UN’s Sustainable Development Goals and the Paris Agreement, industrial organizations need to implement digital solutions as part of their sustainability strategies. Embracing these technologies at all levels – from the boardroom to the facility floor – is key, as every member of the industrial workforce can become a better decision-maker when it comes to sustainability.”

New-Tech Magazine Europe l 17

Level-Setting DAC Calibration for ATE Pin Electronics

Minhaaz Shaik, Product Applications Engineer

Abstract This article provides the methodology to calibrate digital-to-analog converters (DACs) specifically for pin electronic drivers, comparators, load, PMU, and DPS. DACs have nonlinear properties such as differential nonlinearity (DNL) and integral nonlinearity (INL), which can be minimized with the use of gain and offset adjustments. This article describes how to make those corrections for improved level-setting performance. Introduction Automated test equipment (ATE) descr ibes test ing apparatuses designed to perform a single or sequence of tests on one device or multiple devices at a time. Different types of ATE tests electronics, hardware, and semi conductor devices. Timing devices, DACs, ADCs, multiplexers, relays, and switches are

the supporting blocks in the tester or ATE system. These pin electronic devices can deliver signals and power with precise voltages and currents. These precision signals are configured by the level-setting DACs. In the ATE portfolio, some pin electronic devices have calibration registers, and some calibration settings are stored off- chip. This article describes the DACs’ function, errors, and calibration via gain and offset adjustments. Digital-to-Analog Converter (DAC) A DAC is a type of data converter that converts digital inputs to corresponding analog output levels. An N-bit DAC can support 2N output levels. A higher number of bits corresponds to a higher DAC output resolution. First, the N-bit digital input is provided to a DAC serial register. The voltage switch and resistor summing network converts the digital inputs to analog output levels. The transfer characteristics of the DAC plot are

shown in Figure 2. For a 3-bit DAC, 23 digital input yields eight analog output levels. DAC Errors In the real world, converters are not ideal. Because of the variance in resistance values, interpolation, and sampling, the DAC transfer function will not be a straight line, or linear. These errors are namely referred to as differential nonlinearity (DNL) and integral nonlinearity (INL). DNL is the maximum deviation of the output levels from ideal step sizes. It is derived from the difference between two successive output voltage levels. INL is the maximum deviation of the input/output characteristic from the ideal transfer function. With the gain and offset corrections, the INL errors can be reduced. The INL in Figure 3 shows the deviation between actual transfer function and ideal transfer function. The gain error

18 l New-Tech Magazine Europe

of the DAC indicates how well the slope of the linear approximation of the actual transfer function matches the slope of the ideal transfer function. Adjusting the gain will affect the angle of the linear approximation when graphed. The offset error is the difference between the measured value and chosen desired zero-offset point. Adjusting the offset will shift the entire linear approximation up or down accordingly. The INL of a single code is the sum of both gain error and offset error at any given point. After calibration, the transfer function can be a line drawn between end points once the gain and offset errors have been minimized. Calibration Routine The user can establish a calibration routine to reduce DAC nonlinearities using gain and offset corrections. The following procedure explains the step-by- step process of an example calibration routine. For an N-bit DAC: Gain correction (GC): DACs tend to become less linear at the lowest and highest binary values. Therefore, it is recommended to choose calibration points within 5% to 10% in between the outer binary values or EC table recommended calibration points. For the following calculation, we assume 5% calibration points. Set the DAC input to 5% above the lowest binary value. Calculate the expected voltage output and record it as IDEAL1. Measure the output voltage and record it as MEAS1. Set the DAC input 5% below the highest binary value. Calculate and record IDEAL2. Measure the output voltage and record it as MEAS2.

Figure 1: A digital-to-analog converter (DAC) block diagram.

Figure 2: Ideal transfer function of a 3-bit DAC.

Figure 3: INL error transfer function.

Offset correction (OC): The desired zero-offset point varies by application. The user should define the best value based on their application. Some users may prefer to use zero volts to get an exact ground reference point. Some users prefer to use the midpoint of their operating range to minimize the overall INL error.

New-Tech Magazine Europe l 19

Apply the gain correction of the DAC to the slope of the voltage-to- code equation to establish unity gain. Choose the desired zero-offset voltage point and record it as IDEAL3. Calculate the code using your updated vol tage-to-code equation. Program your calculated code, then measure the output voltage and record it as MEAS3.

Figure 4: DAC-level setup of the MAX32007 using eval board software.

Example 1 Consider the MAX32007, an octal DCL with integrated level-setting DACs and PMU switches. The MAX32007 has internal DACs for level-setting VDH, VDL, VDT/VCOM, VCH, VCL, VCPH, and VCPL. These DACs do not have internal calibration registers. To calibrate the DACs, follow this procedure: Power up the MAX32007 evaluation (EV) kit by following the instructions in the EV kit data sheet. Connect the SMB connectors DATA0A and NTRM0A to 1.2 V. Connect the SMB connectors NDATA0A and TRM0A to ground through a 50 Ω terminator. Connect the EV kit to a Windows® 10 PC through a USB cable. Open the MAX32007 EV kit software (GUI).

Apply VDH = –1.5 V and measure the output voltage value. Apply VDH = 4.5 V and measure the output voltage value. Gain correction = Difference between measure output voltage values/ difference between ideal values. For example, (4.501 – (–1.497)) / (4.5 – (–1.5)) = 0.999667 After applying gain correction,

To apply gain correction, open Menu › Options › Calibration, as shown in Figure 5.

Figure 5: Calibration menu of the MAX32007 DAC.

Apply the DAC voltage levels and driver settings as shown in Figure 4. Note that the lowest operating VDH DAC value is –1.5 V, the highest operating value is 4.5 V; in this case, the zero-offset point value is 1.5 V.

Figure 6: INL error correction for DACs with calibration registers.

20 l New-Tech Magazine Europe

Apply VDH = 1.5 V (with gain correction code) and measure the output voltage value. Offset correction = Measure output value – Ideal value. For example (1.502 – 1.5) = 0.002. After applying gain and offset correction, Example 2 Consider the MAX9979, a dual DCL with integrated level-setting DACs and PMU. The MAX9979 has internal DACs for level-setting VDH, VDL, VDT, VCH, VCL, VCPH, VCPL, VCOM, VLDH, VLDL, VIN, VIOS, CLAMPHI/VHH, and CLAMPLO. These DACs have internal calibration registers. In Example 1, the DAC input codes are adjusted to minimize the INL error. In Example 2, the DAC input code remains the same and the calibration registers adjust the output stage buffer to minimize the INL errors, as depicted in Figure 6. To calibrate the DACs, use the following procedure: Power up the MAX9979 EV kit by following the instructions in the EV kit data sheet. Connect the SMB connectors DATA0A and NTRM0A to 1.2 V. Connect the SMB connectors NDATA0A and TRM0A to ground through the 50 Ω terminator. Connect the EV kit to a Windows 10 PC through a USB cable. Open the MAX9979 EV kit software (GUI).

Figure 7: DAC-level setup of the MAX9979 using the eval board software.

highest recommended value is 4.5 V, while the zero-offset point value is at 1.5 V. Apply VDH = –1.45 V and measure the output voltage value. Apply VDH = 6.5 V and measure the output voltage value. Gain correction = Difference between measure output voltage values/ difference between ideal values. For example, (6.501 V – (–1.455 V))/(6.5 V – (–1.45 V)) = 1.0007 V. After applying gain correction, Note: gain and offset corrections can be applied on Menu › Options › Change › Calibration, as shown in Figure 8. Conversion of gain and offset corrections to gain and offset codes are given in the MAX9979 data sheet. About the Author Minhaaz Shaik is a member of the technical staff at Analog Devices with more than five years of experience as an applications/ systems engineer in the analog and mixed-signal domain. Minhaaz mainly focuses on product lines such as automated test equipment (ATE) pin electronics, ADCs, DACs, and

Figure 8: Calibration register setup for the MAX9979.

supervisory and interface ICs. She is a highly skilled professional in electronic system design, lab evaluat ion, automation, customer support, and technical writing, and has significant knowledge in SPICE simulations and circuit design. She can be reached at minhaaz.shaik@analog.com.

Apply the DAC voltage levels and driver settings as shown in Figure 7. Note that the VDH DAC lowest recommended value is –1.5 V, the

New-Tech Magazine Europe l 21

Exploring liquid-based memories for ultrahigh-density storage applications

Maarten Rosmeulen, IMEC

A slowdown of the storage density scaling trend Today’s memory landscape comprises diverse types of memory, each of which plays its part in storing the data and feeding them back and forth to the computational part of the electronic system. In traditional computer hierarchies, fast and more expensive active memories (static random access memory (SRAM) and dynamic RAM (DRAM)) are distinguished from higher- latency and lower-cost storage solutions. Storing large amounts of data is primarily accomplished by NAND-Flash, hard disk drive (HDD), and tape technologies. While tape storage remains limited to long-term archiving, HDD and NAND- Flash are used for online and nearline storage applications: they both need to be accessed more frequently than tapes, with access times ranging from microseconds to seconds. NAND-Flash offers the lowest latency and power consumption of these two storage types. This non-volatile memory is present in all major electronic

end-use markets, such as smartphones, servers, PCs, tablets, and USB drives. Researchers have been able to significantly improve the bit density of the various storage solutions throughout the years to keep up with the growing demand for bits per volume. However, for some years now, HDD technology has not been able to follow the historical productivity trendline. A similar time lag is expected for NAND-Flash technology. 3D-NAND-Flash is projected to reach storage densities of up to 70Gbit/mm2 by 2029, which is a slowing down of circa four years with respect to the historical density scaling roadmap. Entering the post-NAND era After NAND-Flash scaling has saturated, we expect different storage technologies to co-exist, each trading off size, energy consumption, latency, and cost. New concepts for storage are being investigated, not to replace the existing storage solutions but to complement them in the latency/productivity space. Think

about DNA storage, targeting low-cost, ultrahigh-density but slow archival applications (such as preservation of (surveillance) video, medical and scientific data), or ferro-electric memory technology, projected to find its place in the lower-latency storage market segment. All these memories will be organized in different tiers and will jointly address the storage needs of the >100 zettabyte data era. In this article, we propose two new liquid-based storage concepts – colloidal and electrolithic memory – with the potential for ultrahigh-density nearline storage applications. These storage solutions could, for example, make archived ‘inactive’ data such as email archives, image & sound files, or other large documents accessible to users within seconds. From 2030 on, they might find their place between HDD and tapes, at significantly higher bit per volume but slower than 3D-NAND- Flash.

22 l New-Tech Magazine Europe

Cover Image credit: IMEC

Increasing the bit density requires new ways to address memory cells We believe there is a fundamental reason why it is challenging to scale further the bit densities of conventional solid-state memories (such as SRAM, DRAM, or 3D-NAND-Flash) cost-efficiently. In all these memories, the memory cells are organized in two- or three-dimensional arrays, at the cross-points of word- and bitlines. Each cell minimally consists of a storage element and an access device. The access device – usually a transistor or a diode – connects the storage element to at least two wires needed for selecting, reading, and writing the memory cell. The scaling challenge does not relate to the storage element itself (storage elements the size of a single molecule have already been demonstrated) but rather to the access device and its wiring. Cells are at least 2Fx2F (4F2) in size, with F the minimum feature size (for example, the wordline half-pitch) determined by the (expensive) lithography step used for patterning the wires. This configuration with one access device for each storage element makes it challenging to develop cost-efficient high- density solutions and store more than a few bits per cell (with 4-bit NAND-Flash cells currently being the maximum). A different strategy is pursued by HDD and tape storage technologies. Here, a significantly smaller number of read/write access devices connect to a larger un- patterned area that serves as the storage medium. This leads to higher densities and lower cost per bit than NAND-Flash. But also to slower, bulkier and energy- consuming solutions – as the reading heads must be mechanically positioned over a large area. Disruptive solutions couple a dense array of access devices to a volumetric storage medium By reconciling the best of both worlds, new approaches can be found for making

Figure 1: Indicative overview of today’s main memory technologies and their application domains, illustrating the trade-off between latency and productivity (also presented at IMW 2022).

ultrahigh-density storage devices at an affordable cost per bit that operate faster than, for example, tapes. Why not make a dense array of access devices that connect to a volumetric storage medium? Inspired by advances in life sciences, this storage medium could be a liquid containing ions, molecules, or (nano-)particles, which can be manipulated and moved in larger volumes to an access device that is part of a dense array. This approach would enable multi-bit operation, with significantly fewer access devices, wires, and lithography steps needed per bit. The high-density potential of this new approach has attracted interest from industry, and several liquid-based concepts are being investigated worldwide. Below, we propose two new liquid-based concepts with long-term potential for nearline storage, targeting (sub-)second access times. In this article, the focus is on their operating principle and first experimental results. More details were

presented at IMW 2022 [1], and work on the electrolithic memory was recently published in IEEE Transactions on Electron Devices [2]. Colloidal memory: manipulating nanoparticles A first liquid-based memory concept introduced by imec is referred to as the colloidal memory. It nicely shows how liquid (e.g., water) can be used as the volumetric storage medium and dissolved nanoparticles (the colloid) as carriers of the data symbols. The idea is to use a colloid of (at least) two types of nanoparticles (A and B) contained in a reservoir. This reservoir is attached to an array of capillaries, into which the nanoparticles can be inserted. Provided that the nanoparticles are only slightly smaller than the diameter of the capillaries, the sequence in which the particles (the bits) are entered into the capillaries can be preserved. It is

Figure 2: Three different types of addressing employed by memory technologies (also presented at IMW 2022).

New-Tech Magazine Europe l 23