New-Tech Europe Magazine | Sep 2019 | Digital Edition

initial, more relaxed 64nm pitch. For these EUV-based multi-patterning approaches, line-edge roughness however remains an important issue. The team believes that this LER can be further reduced, e.g. by choosing the correct resist material and improving on resist smoothening. eSALELE: a different approach to integrate blocks All three multi-patterning approaches have one thing in common: first, the lines and trenches are printed, and later on, blocks are added – using e.g. a self- aligned block approach. The imec team also investigated a different approach using EUVL – called eSALELE – where lines and blocks are defined throughout the same process flow. Besides a relatively high LER, an additional drawback of this approach is the use of four EUV masks (two for the lines and two for the blocks) – making this concept more costly. Stefan Decoster: “But the main advantage of the eSALELE approach is the flexibility in design, and the avoidance of ‘dummy’ metal lines – printed lines that are not really needed for the chips operation. Avoiding these lines is beneficial for the RC delay and power consumption in the back-end-of- line.” The team is currently exploring the feasibility of printing 16nm pitch lines with the eSALELE technique. Single exposure EUVL entering the memory field: the case of STT-MRAM Due to its high writing and reading speed, STT-MRAM has recently emerged as a promising candidate for replacing SRAM-based last-level cache memories. The core element of an STT-MRAM device is a pillar-like magnetic tunnel junction, in which an insulating layer is sandwiched between two thin ferromagnetic layers which are the fixed and the free layers. The magnetic tunnel junction can exist

Figure 2: Top-down SEM images for the three patterning flows to enable 16nm pitch gratings: (top) EUV-based SADP, (middle) EUV-based SAQP and (bottom) 193nm immersion-based SAOP. Line-edge roughness values for all three options are shown for the final patterns of 8nm lines and trenches [as presented at 2019 SPIE Advanced Lithography].

in two different resistance states: a low resistance state (LRS, with the magnetization of the two magnetic layers in parallel) and a high resistance state (HRS, with the magnetization in an antiparallel state). Writing of the memory cell is performed by switching the magnetization for the free magnetic layer, by means of a current that is injected into the magnetic tunnel junction. The read operation relies on tunnel magnetoresistance (TMR), which is a function of the resistance difference between the two resistance states. From immersion lithography to single exposure EUVL So far, the pillars – i.e. the stacked layers forming the magnetic tunnel junction – have been patterned with 193nm immersion lithography to achieve 200nm, and, later on, 100nm pitch pillar pitches. Murat Pak, R&D engineer at imec: “But in order to meet the high-density requirement for future memories, we need tighter pitches such as 50nm or less – with pillar diameters of around 20nm (i.e., the pillar CD after full patterning). These aggressive pitches can no longer be achieved with immersion lithography, and this

highlights the need for introducing single exposure EUVL.” Introducing LCDU as the most critical metric At these small dimensions, the impact of roughness and stochastic failures can however no longer be neglected – calling for improved patterning techniques. “For this memory application, the most critical parameter turns out to be the local CD uniformity (or LCDU), which is a measure for the pillar roughness,” explains Murat Pak. “This LCDU will obviously impact the resistance variation, and hence the read performance of the STT-MRAM cell. Therefore, ensuring a good LCDU is critical in STT-MRAM manufacturing.” In order to optimize the LCDU of the magnetic tunnel junction pillars, different EUV litho processes have been proposed and compared. Murat Pak: “First, we considered different resists, including the well-known chemically amplified resist (or CAR, which was initially optimized for 193nm immersion lithography), and two different MCR (or metal containing) resists. Second, our team screened different underlayers (including spin-on carbon and spin-on glass) – which is the layer underneath

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