New-Tech Europe Magazine | Sep 2019 | Digital Edition

the resist – and studied their impact on the performance of the resist material. And finally, we studied different tonalities, in particular a negative tone CAR resist (creating pillars) and a positive tone resist in combination with a tone reversal process (‘turning’ holes into pillars).” The team also checked if the targeted improvements on the LCDU were transferred to the etch process. For all experiments, exposures have been performed using an ASML TWINSCAN NXE:3300B. Three promising approaches As a main conclusion, the two most promising approaches in terms of LCDU have been obtained with one type of MCR resist. A third option – making use of the tone reversal process – also performed well, mainly in terms of pillar LCDU as well. “For all three approaches, we obtained an improvement above 20% for the LCDU performance,” adds Murat Pak. “This is an important step towards the targeted LCDU of 1.55nm after full patterning.” For these promising litho process options, other performance metrics such as process window analysis, pillar circularity and critical dimension uniformity (i.e. CD uniformity within one or different wafers) have been verified as well. In summary In this article, various EUVL patterning approaches have been proposed for future logic and memory (i.e., SST- MRAM) applications. For logic, the performance of EUV-based SADP, EUV- based SAQP and EUV-based SALELE were compared with immersion-based SAOP. All options have the potential of printing metal line pitches and trenches as aggressive as 16nm. However, trade-offs have to be made in terms of process complexity, cost- of-ownership, freedom in design, and line-edge roughness. For SST-MRAM, three different EUV-based approaches have been identified for printing 50nm

Figure 3: (Left) Demonstration of the resistance states and the allowed variations; (right) X-SEM image of the pillars

pitch magnetic tunnel junction pillars, with promising LCDU performance. About Stefan Decoster Stefan Decoster holds an M.Sc. degree in physics from KU Leuven, where he also received a PhD degree in physics in 2009 on ion implantation-related lattice damage in semiconductors. After working one year as a post-doctoral researcher at the National University of Australia in Canberra, he joined imec in 2012 as an R&D dry etch engineer. He is specialized in back-end-of-line (BEOL) dry etch processing, with a strong focus on dimensional scaling through multi-patterning schemes and self-aligned patterning approaches. About Murat PAK Murat PAK was born in Turkey, in 1986. He received the B.S. degree

in electronics engineering from the Istanbul Technical University, Turkey, in 2008. In 2011, he has received the M.Sc. degree in electrical and electronics engineering from the Bogazici University. The master thesis has been completed in the Department of Electrical Engineering (ESAT) of KU Leuven, Belgium. In 2010, he has joined the Semiconductor Technologies Research Lab of the National Scientific Council of Turkey, Tubitak, as a research engineer and worked there as a senior research engineer until early 2017, when he joined imec as an R&D engineer. Both in Tubitak and imec, he has focused on the process development of the lithography steps of semiconductor manufacturing. At imec, he mainly focuses on the litho development of the memory projects.

Figure 4: Illustration of the tone reversal process: (left) holes obtained with a posi- tive tone CAR resist and (right) pillars obtained after tone reversal (as presented at 2019 SPIE Advanced Lithography).

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